Signal Flow Graph – The Right Presentation of an Electrical Circuit
F. R. Rasim, S. M. Sattler
ICCESEN 2016, 19. - 24.10.2016, Antalya, Türkei

A Real-World Model of Partially Defined Logic
G. Uygur, S. M. Sattler
12th International Workshop on Boolean Problems, 22. - 23.09.2016, Freiberg

Boolean Discrete Event Modeling and Composition of Circuit Structures
G. Uygur, S. M. Sattler
12th International Workshop on Boolean Problems, 22. - 23.09.2016, Freiberg

A New Approach for Modeling Inconsistencies in Digital-Assisted Analog Design
G. Uygur, S. Sattler
JETTA (Journal of Electronic Testing), August 2016, Volume 32, Issue 4, pp 491–503, DOI

Zuordnungsstruktur von Signalzuführungen zwischen Testsystem und Testobjekt
F. Babba, G. Uygur, W. Sörgel, S. M. Sattler
DASS 2016, 10. - 11.05.2016, Cottbus

Analyse von Testergebnissen eines Systems und Prüfung dessen Zuverlässigkeit
M. Denguir, S. M. Sattler
DASS 2016, 10. - 11.05.2016, Cottbus

Language Based Modeling for Asynchronous Discrete Event Systems
G. Uygur, S. M. Sattler
AmE 2016, 01. - 02.03.2016, Dortmund

Theoretical Framework for Asynchronous Feedback Network Under Balance (NUB)
G. Uygur, L. Gries, S. Sattler
SMACD 2015, 07. - 09.09.2015, Istanbul, Türkei
IEEE, 2015, pp. 1 - 4, DOI

Structure Preserving Modeling for Safety Critical Systems
G. Uygur, S. Sattler
IMSTW 2015, 24. - 26.06.2015, Paris, Frankreich
IEEE, 2015, pp. 1 - 6, DOI

An Automatic Test Cell Operation to Serve Multiple Users and Products Concurrently
S. Sattler, P. Muhmenthaler
TuZ 2015, 01. - 03.03.2015, Stift Urach - Bad Urach

Strukturtreue Modellierung sicherheitskritischer Systeme
G. Uygur, F. R. Rasim, M. Özgül, S. M. Sattler
AmE 2015, 24. - 25.02.2015, Dortmund