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Zur Parallelen Komposition von Automaten
G. Uygur
Doktorarbeit, FAU Erlangen-Nürnberg, 18.12. 2018, PDF

Structure-Preserving Modelling of Real Circuits based on Signal Flow Graph
M. Denguir, S. M. Sattler
International Journal of Electronic Design and Test (JEDT) Vol.1 No.1, PDF

Early Failures Diagnosis based on Multi-Dimensional Analysis and Separation of High-Dimensional Test Results on an Electronic System
M. Denguir, N. Denguir, S. M. Sattler
International Journal of Electronic Design and Test (JEDT) Vol.1 No.1, PDF

Non-Linear Method for Separation and Analysis of High-Dimensional Test Results on an Electronic System
M. Denguir, N. Denguir, S. M. Sattler
International Journal of Electronic Design and Test (JEDT) Vol.1 No.1, PDF

Fehlersuche innerhalb des μ-Controllers vom Typ PIC32MX
Fault tracing within the μ-Controller PIC32MX
F. Babba, S. M. Sattler
Analog 2018, 13. - 14.09.2018, München-Neubiberg

Test Data Modeling and Implementation with Enhanced Accuracy for the Diagnosis of a DUT provided with Real-World Failure Models
G. Uygur, W. Magerl, W. Sörgel, S. M. Sattler
Workshop on Metrology for AeroSpace 2018, 20. - 22.07.2018, Rome, Italy

µC-Based ATE for Testing a DUT provided with Real-World Failure Models
G. Uygur, W. Magerl, W. Sörgel, S. M. Sattler
AmE 2018, 07. - 08.03.2018, Dortmund

A Real-World Model of Partially Defined Logic
G. Uygur, S. M. Sattler
Further Improvements in the Boolean Domain, Cambridge Scholars Publishing,
ISBN-13: 978-1-5275-0371-7, 87-97 ff, 01.01.2018

Boolean Discrete Event Modeling of Circuit Structures
G. Uygur, S. M. Sattler
Further Improvements in the Boolean Domain, Cambridge Scholars Publishing,
ISBN-13: 978-1-5275-0371-7, 269-281 ff, 01.01.2018

Signal Flow Graph – The Right Presentation of an Electrical Circuit
F. R. Rasim, S. M. Sattler
European Journal of Science and Technology (EJOSAT Journal) 2018, Special Issue, pp. 65-69, PDF

Structure-Preserving Modelling of Safety-Critical Combinational Circuits
F. R. Rasim, S. M. Sattler
ASTES Journal 2018, Volume 3, Issue 1, 472-482 ff, DOI

Mealy-to-Moore Transformation - A State Stable Design of Automata
M. Özgül, F. Deeg, S. M. Sattler
Special Issue on Advancement in Engineering Technology 2017, 162-174 ff, DOI

Analysis of Electronic Circuits with the Signal Flow Graph Method
F. R. Rasim, S. M. Sattler
Journal of Computer and Communications 2017, 261-274 ff, DOI

Structure-Preserving Modeling for Safety Critical Digital Circuits
F. R. Rasim, S. M. Sattler
ICCESEN 2017, 04. - 08.10.2017, Antalya, Türkei

Strukturtreue Modellierung anhand von Signalflussgraphen
M. Denguir, G. Uygur, S. Sattler, B. Cella, M. Schmidt, T. Egelhofer, B. Scheffold
ZuE 2017, 18. - 20.09.2017, Cottbus

TAP-Controller Modellierung mit Signalflussgraphen
JTAG TAP Controller Modeling Using Fignal Flow Graph
F. Babba, S. M. Sattler
ZuE 2017, 18. - 20.09.2017, Cottbus

A Dimensionality-Reduction Method for Test Data - Fault Diagnosis
M. Denguir, S. M. Sattler
IMSTW 2017, 03. - 05.07.2017, Thessaloniki, Greece

Verification and Test of Real Circuits - Structure-Preserving Modelling based on Signal Flow Graph
M. Denguir, S. M. Sattler
IMSTW 2017, 03. - 05.07.2017, Thessaloniki, Greece

Structure-Preserving Modeling of Safety-Critical Combinational Circuits
F. R. Rasim, C. Kocar, S. M. Sattler
DDECS 2017, 19. - 21.04.2017, Dresden

Mealy-to-Moore Transformation
M. Özgül, F. Deeg, S. M. Sattler
DDECS 2017, 19. - 21.04.2017, Dresden

Mealy-to-Moore Transformation in Safety-Critical Systems
M. Özgül, F. Deeg, S. M. Sattler
AmE 2017, 07. - 08.03.2017, Dortmund

 

 

 

 

 

 

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