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Defects, Faults, and Errors – Approaches to Cross-Layer Fault-Tolerance
(Tutorial Workshop in the frame of the DFG Schwerpunktprogramm 1500: Dependability of Embedded Systems)

Mehdi Tahoori, Karlsruhe Institute of Technology (KIT)
Hans-Joachim Wunderlich, Institut für Technische Informatik, Universität Stuttgart

As VLSI fabrication technologies progress further into the nanometer scale, known and new defect mechanisms of semiconductors not only appear during the manufacturing phase, but may occur during the operation of systems and impair their function in the field. These reliability failures processes manifest themselves as temporary or permanent faults during the lifetime of the system. Without proper estimation of their impact and according counter-measures at appropriate levels, dependability in the field and lifetime of the system may be significantly reduced. This tutorial presents an introduction to relevant VLSI defect mechanisms, their manifestation and modeling at the appropriate abstraction level. Efficient counter-measures typically exploit time, information, structural redundancy or a combination thereof, to tolerate, detect or correct impaired behavior. The discussed methods are applied at electrical, gate and RT level, up to software and system level.

Mehdi B. Tahoori a full professor and Chair of Dependable Nano-Computing (CDNC) at the Institute of Computer Science & Engineering, Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany. Before that he was an associate professor of Electrical and Computer Engineering at Northeastern University, Boston, USA. He received his Ph.D. and M.S. in Electrical Engineering from Stanford University in 2003 and 2002, respectively, and B.S. in Computer Engineering from Sharif University of Technology, Tehran, Iran in 2000. He has authored/co-authored more than 100 research papers on various aspects of dependable computing, VLSI testing and emerging nanotechnologies. Dr. Tahoori has served as the program committee member of various conferences, symposia, and workshops in his fields of research. He is an associate editor of ACM journal of Emerging Technologies for Computing and Chair of ACM SIGDA Technical Committee on Test and Reliability. He was a recipient of US National Science Foundation (NSF) Early Faculty Development (CAREER) award.

Hans-Joachim Wunderlich ist Professor und Geschäftsführender Direktor des Instituts für Technische Informatik der Universität Stuttgart. Er studierte Mathematik und Philosophie an den Universitäten Konstanz und Freiburg, promovierte 1986 und habilitierte sich 1990 an der Universität Karlsruhe in Informatik. Seine Forschungsschwerpunkte sind Entwurf und Test digitaler Schaltungen und Systeme, Zuverlässigkeit und Fehlertoleranz. Er ist Autor und Ko-Autor von über 180 Publikationen und erhielt im Jahr 2000 den Landeslehrpreis von Baden-Württemberg. Er war Tagungsleiter und mehrere Jahre Vorsitzender des Programmkomitees des IEEE European Test Symposiums, derzeit ist er Vorsitzender des Steuerkomitees. Hans-Joachim Wunderlich ist Sprecher der GI/GMM/ITG Fachgruppe “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Golden Core Member der IEEE Computer Society und “IEEE Fellow for contributions to very-large-scale-integration circuit testing and fault tolerance”.


Hot Topics in Analog Design Automation for Yield and Reliability
Helmut E. Gräb, Institute for Electronic Design Automation, Technical University Munich, Germany

We will first take a look at several issues of analog sizing. The focus will be on adequate mathematical problem formulations, starting from the general multi-objective sizing problem. Then, statistically distributed parameters and range-valued parameters will be included to obtain the scalar problems of yield optimization and design centering. This will be extended to Pareto optimization considering these parameter tolerances. Second, we will review some developments in important tasks of analog design automation: discrete analog sizing, sizing for reliability, sizing with in-loop-layout, analog layout synthesis, analog structural design. Third, we will discuss possible reasons why it took about 30 years until analog design-for-yield tools have become part of commercially available EDA tools, why hardly any analog EDA tool on the market beyond circuit simulation is really established in practice yet, and why there is this gap between the doubtlessly existing needs for analog EDA and the lacking industrial application.

Helmut Gräb got his Dipl.-Ing., Dr.-Ing., and habilitation degrees from Technical University Munich in 1986, 1993 and 2008, respectively. He was with Siemens Corporation, Munich, from 1986 to 1987, where he was involved in the design of DRAMs. Since 1987, he has been with the Institute of Electronic Design Automation, TUM, where he has been the head of a research group since 1993. His research interests are in design automation for analog and mixed-signal circuits. Dr. Gräb has, for instance, served as a Member of the Executive Committee and Tutorial Chair of the ICCAD conference, as a Member or Chair of the Analog Program Subcommittees of the ICCAD, DAC, and D.A.T.E conferences, as Associate Editor of the IEEE TCAS-II and IEEE TCAD, and as a Member of the Technical Advisory Board of MunEDA GmbH Munich, which he co-founded. He was the recipient of the 2008 prize of the Information Technology Society (ITG) of the Association for Electrical, Electronic and Information Technologies (VDE), of the 2004 Best Teaching Award of the TUM EE Faculty Students Association, of the 3rd prize of the 1996 Munich Business Plan Contest.


Technology Trends in VLSI and Impact on Reliability and Test
Shekhar Borkar, Intel Corporation, USA

As technology continues to scale in the nanoscale regime, it's the same physics that helped you in the past, now poses major challenges in design, reliability, and test. Future designs will have to comprehend them, and incorporate reliability and test into the design from day one. Traditional system level reliability techniques will be ill suited and will have to morph towards resiliency. This course will address all of these challenges.

Shekhar Borkar is an Intel Fellow, an IEEE Fellow, director of Academic Programs and Research, and director of Exascale research in Intel Labs. He holds MSEE from University of Notre Dame and MSc in Physics from University of Bombay. His research interests are low power, high performance digital circuits.

 

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Das Tutorial "Hot Topics in Analog Design Automation for Yield and Reliability" findet leider nicht statt. Registrierungen für die Tagung können auch noch vor Ort erfolgen . . .

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