Self-Locking Domino Logic Pipelines: Application in RISC-V Architectures in FPGA
F. Deeg, X. Chen, S. M. Sattler
Journal of Biosensors and Bioelectronics Research, Nov. 2024, PDF
Self-locking Domino Logic Pipelined Controller for RISC-V in FPGA
F. Deeg, X. Wu, S. M. Sattler
8th Annual International Conference on Electrical Engineering 22. - 26.7.2024, Athen, PDF
Self-Locked Asynchronous Controller for RISC-V Architecture on FPGA
F. Deeg, S. M. Sattler
AmE 2024 14. - 15.3.2024, Dortmund, PDF
Verification of Function Stable Muller C-element in FPGA
F. Deeg, S. M. Sattler
AmE 2023 15. - 16.6.2023, Dortmund, PDF
Dynamic Effects in Asynchronous Circuits
F. Deeg, J. Zhu, S. M. Sattler
AmE 2022 29. - 30.9.2022, Dortmund, PDF
Electronic Circuit Analysis
F. R. Rasim, M. Tadeusiewicz et al.
scitus academics, 2021, PDF
Asynchronous Design
F. Deeg, J. Zhu, S. M. Sattler
AmE 2020 10. - 11.3.2020, Dortmund, PDF
Formale Verifikationsmethode für reale Schaltungen und Systeme
M. Denguir
Doktorarbeit, FAU Erlangen-Nürnberg, 08.08.2019, PDF